来源：hpcwire.com
原英文标题：《RISC-V Opens the Door on 48-bit Computing》
There’s a growing interest among silicon providers backing RISC-V to introduce 48-bit computing in custom chips to meet their specific requirements.
The 48-bit long instructions focus is more as a middle ground between 32-bit and 64-bit, which has largely been the focus of chips and instruction sets until now.
“RISC-V is not pushing any 48-bit instructions right now. But there are some members who are doing custom instructions that are 48-bit… and it is mostly driven by immediate values,” said Mark Himelstein, chief technology officer at RISC-V International.
RISC-V is an open-source instruction set architecture that companies can license for free and then modify to their own needs.
The RISC-V design is modular, meaning that companies can add or subtract modules depending on their requirements. The instruction set is a common tissue on which compute cores – which could be for graphics, artificial intelligence, vector cryptography, etc. – can be linked.
SiFive has developed its own RISC-V processor called the P650 which it has compared to Arm’s Cortex-77 chip. Intel is also working with Barcelona Supercomputing Centre to develop a RISC-V high-performance chip, and is investing billions to make chips based on all major architectures including RISC-V.
The RISC-V architecture is popular in controllers and embedded applications, which are largely 16-bit and 32-bit. Himelstein said that 48-bit instructions may be gathering steam in embedded computing. He added there also conversations on 128-bit instructions in the RISC-V community.
Companies had to rely on getting instruction sets from the big vendors every few years, and either needed a lot of money or influence to get customized chips. RISC-V cuts that reliance and provides a free framework so companies build chips to meet their own computing needs, Himelstein said.
“When you want to add some big prime number or something to a register, that’s harder, because you’ve run out of bits and places to put them. The people who are doing 48-bit have a very large immediate field. The reason they want to do that is their only other choice is to load that value from memory into a register and then add it. If they have it as part of the instruction stream, they don’t have to do that. And in certain workloads, that’s a benefit,” Himelstein said.
The focus on 48-bit instructions is to move up from 32-bit, but not get to 64-bit, chip experts said.
The jump to 48-bits long instructions would make sense if someone wanted more encoding space, and adding new instructions could be helpful, said David Kanter, an analyst at Real World Technologies.
A main value proposition of RISC-V are those custom instructions.
“I’m guessing the community just ran out of room and needs more,” Kanter said.
The 48-bit instructions are non-standard, and they have an opcode format that has a big immediate.
“The same way today we allow the mingling of 16-bit and 32-bit instructions, they allow the mingling of 16-bit, 32-bit and 48-bit instructions. It’s in the normal instruction stream,” Himelstein said.
RISC-V is trying to build a simple and elegant modular design, and also trying to reduce fragmentation with input from the community. The goal is not to repeat the mistakes from the past.
“MIPS started as simple and elegant and became pretty complex. You had lots of various features in various chips that people tried out over the years that they thought were good or bad, and those have gone by the wayside,” Himelstein said.
RISC-V is down to a standard set of registers which is simple and flat, Himelstein said, adding “we get to sort of stand on the shoulders of giants and learn from their lessons.”
Himelstein wasn’t sure of the applications that RISC-V members would use for 48-bit instructions. Kevin Krewell, an analyst at Tirias Research, wasn’t sure either, but said it could be for storage.
“Some workloads need more than 32 bits, but don’t want to use floating point math because of the extra power and silicon. The other reason could be a very large address space is needed for extremely large data storage,” Krewell said.
Someone would have to want to run memory management in software, Krewell said, adding that “applications processors have dedicated memory management unit (MMU) hardware to manage memory pages. Having a 48-bit data path would allow software to manage large memory arrays without an MMU.”
全文机翻：
支持RISC-V在定制芯片中引入48位计算以满足其特定要求的芯片提供商的兴趣越来越大。
48位长指令的焦点更像是32位和64位之间的中间地带，到目前为止，这在很大程度上一直是芯片和指令集的焦点。
“RISC-V现在没有推送任何48位指令。但是有一些成员正在做48位的自定义指令...它主要是由直接价值驱动的，“RISC-V International首席技术官Mark Himelstein说。
RISC-V是一种开源指令集架构，公司可以免费许可，然后根据自己的需求进行修改。
RISC-V设计是模块化的，这意味着公司可以根据其要求添加或减少模块。指令集是一个公共组织，计算核心可以链接在其上 - 可能用于图形，人工智能，矢量密码学等。
SiFive开发了自己的RISC-V处理器，称为P650，与Arm的Cortex-77芯片进行了比较。英特尔还与巴塞罗那超级计算中心合作开发RISC-V高性能芯片，并正在投资数十亿美元制造基于所有主要架构的芯片，包括RISC-V。
RISC-V架构在控制器和嵌入式应用中很受欢迎，这些应用主要是16位和32位。Himelstein表示，48位指令可能正在嵌入式计算中积聚动力。他还在RISC-V社区中增加了关于128位指令的对话。
公司不得不依靠每隔几年从大型供应商那里获得指令集，并且需要大量资金或影响力才能获得定制芯片。Himelstein说，RISC-V减少了这种依赖性，并提供了一个免费的框架，以便公司构建芯片以满足自己的计算需求。
“当你想在寄存器中添加一些大的素数或其他东西时，这很难，因为你已经用完了放置它们的位和位置。做48位的人有一个非常大的直接领域。他们想要这样做的原因是他们唯一的其他选择是将该值从内存加载到寄存器中，然后添加它。如果他们将其作为指令流的一部分，则不必这样做。在某些工作负载中，这是一个好处，“Himelstein说。
芯片专家表示，对48位指令的重点是从32位向上移动，但不能达到64位。
如果有人想要更多的编码空间，跳转到48位长指令是有意义的，添加新指令可能会有所帮助，Real World Technologies的分析师David Kanter说。
RISC-V的一个主要价值主张是这些自定义指令。
“我猜社区只是用完了空间，需要更多，”坎特说。
48位指令是非标准的，并且它们具有具有很大的立即操作码格式。
“就像今天我们允许16位和32位指令混合一样，它们允许16位，32位和48位指令的混合。它在正常的指令流中，“Himelstein说。
RISC-V正试图构建一个简单而优雅的模块化设计，并试图通过社区的意见来减少碎片化。目标不是重复过去的错误。
“MIPS开始时简单而优雅，变得相当复杂。你在各种芯片中有很多不同的功能，人们多年来尝试了他们认为是好是坏，而这些功能已经被搁置一旁，“Himelstein说。
Himelstein说，RISC-V是一套简单而扁平的标准寄存器，并补充说：“我们可以站在巨人的肩膀上，从他们的教训中吸取教训。
Himelstein不确定RISC-V成员将用于48位指令的应用程序。Tirias Research的分析师凯文·克雷韦尔（Kevin Krewell）也不确定，但他表示，这可能是为了存储。
“有些工作负载需要超过32位，但由于额外的功率和硅，他们不想使用浮点数学。另一个原因可能是非常大的数据存储需要非常大的地址空间，“Krewell说。
Krewell说，必须有人想要在软件中运行内存管理，并补充说：“应用程序处理器具有专用的内存管理单元（MMU）硬件来管理内存页。拥有48位数据路径将允许软件在没有MMU的情况下管理大型内存阵列。 |
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发表于 2022-7-11 15:20
第一台电脑是2G……我说的是硬盘……
