Key upgrades in Xtacking4.0 include:
Centered X-DEC die design: This architectural enhancement improves read/write performance by reducing wordline (WL) capacitance and RC load, cutting WL settling time and current demands.
Backside Source Connect (BSSC): First used in Xtacking3.0, BSSC helps streamline vertical connections, now applied to the 160-layer TLC chip for enhanced performance.
Vertical channel (VC) design: The 20-hole VC design, shared with KIOXIA’s BiCS8 218L, eliminates dummy holes, optimizing the 155 nm pitch for better cell density and efficiency.
Higher bit density and reduced die size: With a die size of 40.44 mm² and a density of 12.66 Gb/mm² for the 512 Gb chip, Xtacking4.0 offers increased storage capacity and performance within a smaller footprint.
Hybrid bonding maturity: This technology, crucial to YMTC’s process, is now more refined and is the backbone of YMTC’s high-density, vertically connected 3D NAND chips.
来源：https://www.techinsights.com/blo ... -3d-nand-technology
技术上还是有提升的 |
楼主: VictorTDD
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发表于 2024-8-20 09:36
